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Q1. What is a multiplexer? Design a 4 to 1 multiplexer using logic gates. Write the truth table

and explain its working principle.

Q2. Construct 4:1 multiplexer using only 2:1 multiplexer.

Q3. Construct 8:1 multiplexer using only 2:1 multiplexer.

Q4. Design 16 to 1 multiplexer using 8 to 1 multiplexer and one 2 to 1 multiplexer.

Q5. Design 32 to 1 multiplexer using 16 to 1 multiplexer and one 2 to 1 multiplexer.

Q6. Mention the differences between decoder and demultiplexer.

Q7. (a) Realize Y A B B C ABC using an 8 to 1 Multiplexer.

Q8. Implement the following Boolean functions using 4:1 multiplexer (MUX):

( ) ( , , , ) (0,1,2,4,6,9,12,14)

( ) ( , , ) (1,3,5,6)

Q9. Implement the Boolean function expressed by SOP:

f A B C D m ( , , , ) (1,2,5,6,9,12) using 8 to 1 MUX.

Q10. Implement the Boolean function:

F A B C D m ( , , , ) (0,1,2,4,5,7,8,9)

using 8 to 1 multiplexers. Draw the logic diagram and

explain the operation. Additional gates can be used if required.

Q11. Realize the following Boolean function:

P f w x y z ( , , , ) (0,1,5,6,7,10,15) using (i) 16:1 MU X (ii) 8:1 MUX (iii) 4:1 MUX 0 1 2 3 4 5 6 7

Q12. Design and implement BCD to excess-3 code converter using four 8:1 multiplexers. Take

MSB ‘A’ as map entered variable(input variable) ‘BCD’ lines as select lines, assuming

f(A,B,C,D) as BCD input.

Q13. Realize a logic circuit for octal to binary encoder.

B0 Q14. Implement a full adder using a 3 to 8 decoder.

Q14. Implement a full adder using a 3 to 8 decoder.

Q15. Implement full adder using IC 74138

Q16. Implement 3 bit binary to gray code conversion by using IC 74139.

Q17. Design a priority encoder for a system with a 3 inputs, the middle bit with highest priority

encoding to 10, the MSB with the next priority encoding to 11, while the LSB with least priority

encoding to 01.

Q18. Design a 4 to 16 line decoder using 2 to 4 line decoder which has the active low outputs as

active low enable input. Explain its operation.

Q19. Write the comparisons between PLA and PAL.

Q20. Design 7-segments decoder using PLA.

Q21. Implement the following function using PLA:

Q22. Draw the PLA circuit and realize the Boolean functions:

Q23. Describe the working principle of 3:8 decoder. Design a circuit that realizes the following

functions using a 3:8 decoder and multi input OR gates.

1 2 ( ) ( , , ) (1,3,7) (ii) ( , , ) (2,3,5) i F A B C m F A B C m

Q24. What is magnitude comparator? Design one bit comparator and write the truth table, logic

circuit using basic gates.

Q25. What is parity generator? Explain with an example.

Q26. What is parity checker? Explain with example.

Q27. Give state transition diagram of SR, D, JK and T flip flops.

Q28. Obtain the characteristic equation of SR, JK, D and T flip flops.

Q29. Explain the operation of a gated SR latch with a logic diagram and truth table.

Q30. Explain the operation of edge triggered ‘SR’ flip flop with the help of a logic diagram and

truth table. Also draw the relevant waveforms.

Q31. Explain the operation of edge triggered ‘D’ flip flop with the help of a logic diagram and

truth table. Also draw the relevant waveforms.

Q32. Explain the working of pulse triggered JK flip flop with typical JK flip flop waveform.

Q33. Explain the working of Master Slave J K flip flops with logic diagram.

Q34. What is contact bounce? With neat diagram, explain the working principles of Switch De bounce circuit.

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Q1. What is a multiplexer? Design a 4 to 1 multiplexer using logic gates. Write the truth tableand explain its working principle.

Q2. Construct 4:1 multiplexer using only 2:1 multiplexer.

Q3. Construct 8:1 multiplexer using only 2:1 multiplexer.

Q4. Design 16 to 1 multiplexer using 8 to 1 multiplexer and one 2 to 1 multiplexer.

Q5. Design 32 to 1 multiplexer using 16 to 1 multiplexer and one 2 to 1 multiplexer.

Q6. Mention the differences between decoder and demultiplexer.

Q7. (a) Realize Y A B B C ABC using an 8 to 1 Multiplexer.

Q8. Implement the following Boolean functions using 4:1 multiplexer (MUX):

( ) ( , , , ) (0,1,2,4,6,9,12,14)

( ) ( , , ) (1,3,5,6)

Q9. Implement the Boolean function expressed by SOP:

f A B C D m ( , , , ) (1,2,5,6,9,12) using 8 to 1 MUX.

Q10. Implement the Boolean function:

F A B C D m ( , , , ) (0,1,2,4,5,7,8,9)

using 8 to 1 multiplexers. Draw the logic diagram and

explain the operation. Additional gates can be used if required.

Q11. Realize the following Boolean function:

P f w x y z ( , , , ) (0,1,5,6,7,10,15) using (i) 16:1 MU X (ii) 8:1 MUX (iii) 4:1 MUX 0 1 2 3 4 5 6 7

Q12. Design and implement BCD to excess-3 code converter using four 8:1 multiplexers. Take

MSB ‘A’ as map entered variable(input variable) ‘BCD’ lines as select lines, assuming

f(A,B,C,D) as BCD input.

Q13. Realize a logic circuit for octal to binary encoder.

B0 Q14. Implement a full adder using a 3 to 8 decoder.

Q14. Implement a full adder using a 3 to 8 decoder.

Q15. Implement full adder using IC 74138

Q16. Implement 3 bit binary to gray code conversion by using IC 74139.

Q17. Design a priority encoder for a system with a 3 inputs, the middle bit with highest priority

encoding to 10, the MSB with the next priority encoding to 11, while the LSB with least priority

encoding to 01.

Q18. Design a 4 to 16 line decoder using 2 to 4 line decoder which has the active low outputs as

active low enable input. Explain its operation.

Q19. Write the comparisons between PLA and PAL.

Q20. Design 7-segments decoder using PLA.

Q21. Implement the following function using PLA:

Q22. Draw the PLA circuit and realize the Boolean functions:

Q23. Describe the working principle of 3:8 decoder. Design a circuit that realizes the following

functions using a 3:8 decoder and multi input OR gates.

1 2 ( ) ( , , ) (1,3,7) (ii) ( , , ) (2,3,5) i F A B C m F A B C m

Q24. What is magnitude comparator? Design one bit comparator and write the truth table, logic

circuit using basic gates.

Q25. What is parity generator? Explain with an example.

Q26. What is parity checker? Explain with example.

Q27. Give state transition diagram of SR, D, JK and T flip flops.

Q28. Obtain the characteristic equation of SR, JK, D and T flip flops.

Q29. Explain the operation of a gated SR latch with a logic diagram and truth table.

Q30. Explain the operation of edge triggered ‘SR’ flip flop with the help of a logic diagram and

truth table. Also draw the relevant waveforms.

Q31. Explain the operation of edge triggered ‘D’ flip flop with the help of a logic diagram and

truth table. Also draw the relevant waveforms.

Q32. Explain the working of pulse triggered JK flip flop with typical JK flip flop waveform.

Q33. Explain the working of Master Slave J K flip flops with logic diagram.

Q34. What is contact bounce? With neat diagram, explain the working principles of Switch De bounce circuit.

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